Boundary-Scan Interconnect Diagnosis (Frontiers in by JosA© T. de Sousa, Peter Y.K. Cheung

By JosA© T. de Sousa, Peter Y.K. Cheung

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Extra info for Boundary-Scan Interconnect Diagnosis (Frontiers in Electronic Testing)

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For technologies that enable direct mounting of silicon dies on both sides of the board, such as tape automated bonding (TAB) or chip on board (COB), this problem becomes even worse. 6 Boundary-scan testing ICT is rapidly becoming obsolete, and a substitute technology has become a major priority. In the 80s, a technology able to fill in this gap began to emerge. This technology was inspired by IC design for testability methods (Williams, 1982) and was called boundary-scan (BS) testing (Maunder and Beenker, 1987).

Behavioral schemes are very popular in the industry. They are simple, effective and can be derived independently from the layout design. The study presented in this chapter draws from the more general fault models discussed in Chapter 2. Compared to previously published analyses, this study is more comprehensive as it takes into account mixed short-open faults of any multiplicity and deals with the problem of fault masking. Procedures for diagnostic analysis and fault isolation are studied. Then, several diagnostic synthesis schemes are analyzed in terms of test vector length and diagnostic capability.

A diagnostic scheme may have different degrees of diagnostic resolution, but must be at least capable of detecting any non-redundant fault, single or multiple. The minimum requirement for test completeness (detection of any fault of any multiplicity) is identified, and the diagnostic properties of the most important diagnostic schemes are analyzed for the fault models considered. A new scheme, the N sequence, has been derived. This scheme is the shortest diagonal independent scheme. 2 The few existing structural methods for interconnect diagnosis are analyzed in the light of the new fault modeling approach.

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